SI Verify is suitable for the analysis of PCB designs during placement phase during which wiring or for post-layout analysis on the finished design.
Seamlessly integrated into the CADSTAR Design suite, CADSTAR SIV utilises the Constraint Manager spreadsheet-style interface that simplifies design navigation and constraint entry for High Speed, Signal Integrity and Power Integrity Analysis.
The graphical Scenario Editor lets you explore alternate design strategies to assess the best approach to meet your design objectives. You can model a virtual prototype using vendor-supplied IBIS models, or generic devices from the built-in library, to evaluate different termination styles and net topologies to achieve the optimum design.
CADSTAR SIV works in both time- and frequency- domain modes to analyse transmission lines parameters, provide fast analysis of reflection and crosstalk, and measure timing and delay characteristics. You have the option of Interactive or Batch modes, returning a range of results including Impedance, Coupled line, S-Parameter, Fast Fourier Transformation and Eye Diagrams, while automatic signal evaluation provides a full range of numeric data points.
Experiment with passive device values or transmission line length using Parameter Sweep to determine optimal values. Passive SPICE models can also be used and equivalent circuit models can be created to model passive parasitic devices.
Layer Stack Definition
The layer stack can be modelled to determine the characteristic impedance of critical transmission lines, accommodating track profile (trapezoid) and advanced construction materials to achieve more accurate results. Frequency-dependent losses are accommodated for enhanced accuracy at higher frequencies.
Don't forget the first 12 months of maintenance are included in your purchase
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|Our Price: £13,650.00|
Product Code: pc-6091-01
In stock, immediate despatch